" Tensor Virtualization Technique to Support Efficient Data Reorganization for CNN Accelerators," DAC 2020 (to appear)
"A Novel CNN(Convolutional Neural Network) Accelerator That Enables Fully-pipelined Execution of Layers," ICCD 2019
"Fast Performance Estimation and Design Space Exploration of Manycore-based Neural Processors," DAC 2019
"C-GOOD: C-code Generation Framework for Optimized On-device Deep Learning," ICCAD 2018
"Joint Optimization of Speed, Accuracy, and Energy for Embedded Image Recognition Systems," DATE 2018
단말용 뉴럴 프로세서 시뮬레이션 및 소프트웨어 최적화 기술,  삼성종합기술원, 2016. 12 - 2020. 10
MIDAP (Memory-In-the DAtapath Processor) 뉴럴 프로세서의 성능 개선 연구, 삼성전자, 2018.5 - 2020.4
이종 하드웨어 가속기를 포함하는 모바일 플랫폼을 위한 시스템 수준의 딥 러닝 추론 최적화 기법, 삼성전자, 2018.3 - 2018.12

"FlexLearn: Fast and Highly Efficient Brain Simulations Using Flexible On-Chip Learning", Eunjin Baek, Hunjun Lee, Youngsok Kim, and Jangwoo Kim, ACM/IEEE International Symposium on Microarchitecture (MICRO), Oct 2019
"MnnFast: A Fast and Scalable System Architecture for Memory-Augmented Neural Networks", Hanhwi Jang, Joonsung Kim, Jae-Eon Jo, Jaewon Lee, and Jangwoo Kim, ACM/IEEE International Symposium on Computer Architecture (ISCA), Jun 2019
"Flexon: A Flexible Digital Neuron for Efficient Spiking Neural Network Simulations"
Dayeol Lee, Gwangmu Lee, Dongup Kwon, Sunghwa Lee, Youngsok Kim, and Jangwoo Kim, ACM/IEEE International Symposium on Computer Architecture (ISCA), Jun 2018
"μLayer: Low Latency On-Device Inference Using Cooperative Single-Layer Acceleration and Processor-Friendly Quantization", Youngsok Kim, Joonsung Kim, Dongju Chae, Daehyun Kim, and Jangwoo Kim, ACM European Conference on Computer Systems (EuroSys), Mar 2019
"FIDR: A Scalable Storage System for Fine-Grain Inline Data Reduction with Efficient Memory Handling", Mohammadamin Ajdari, Wonsik Lee, Pyeongsu Park, Joonsung Kim, and Jangwoo Kim, ACM/IEEE International Symposium on Microarchitecture (MICRO), Oct 2019
인공지능 가상머신: 이종 인공지능의 동시, 고속, 독립 실행을 위한 컴퓨터 구조/삼성미래기술육성사업/2019.6-2022.5
이종 스파이크 뉴런 기반의 인간 두뇌 규모 시뮬레이션을 위한 프로세서 및 시스템 개발/한국연구재단/2017.3-2021.2
대규모 뉴럴 프로세싱을 위한 FPGA 기반의 확장형 시스템 개발/삼성전자/2017.11-2020.10

"Partitioning Compute Units in CNN Acceleration for Statistical Memory Traffic Shaping,"  D. Jung, S. Lee, W. Rhee, and J. Ahn, IEEE Computer Architecture Letters, Vol. 17, No. 1, 2018
뉴럴 프로세싱 시스템 연구, 삼성전자, 2017/11-2020/10
복합 심층학습 응용분야를 위한 가속기 구조 연구, 삼성미래기술육성재단, 2017/12-2019/11

Hawkware: Network Intrusion Detection based on Behavior Analysis with ANNs on an IoT Device, Design Automation Conference (DAC), Jul 2020
DADE: a fast data anomaly detection engine for kernel integrity monitoring, The Journal of Supercomputing, Aug 2019
Real-Time Anomalous Branch Behavior Detection with a GPU-inspired Engine for Machine Learning Models, Design Automation and Test in Europe (DATE), Mar 2019
An SoC Architecture for Learning-Based Online Anomaly Detection on ARM, Design Automation Conference (DAC) WIP, Jun 2018
Mimicry Resilient Program Behavior Modeling with LSTM based Branch Models, DEEP LEARNING AND SECURITY WORKSHOP, May 2018
Behavior-based Malware Detection in HW support, 1억, 삼성전자
AI 포렌식 빅데이터 기반 지능형 보안 위협 분석, 8500만, 서울특별시
Embedded 시스템에서의 (AI 기반) 공격탐지 및 데이터 전송 솔루션, 1억, 삼성전자

Fast and Flexible Deep Learning via Symbolic Graph Execution of Imperative Programs. NSDI 2019.
Parallax: Sparsity-aware Data Parallel Training of Deep Neural Networks. EuroSys 2019.
Apache Nemo: A Framework for Building Distributed Dataflow Optimization Policies. ATC 2019.
PRETZEL: Opening the Black Box of Machine Learning Prediction Serving Systems. OSDI 2018.
Improving the Expressiveness of Deep Learning Frameworks with Recursion. EuroSys 2018.
(SW 스타랩) 다양한 분석을 고속 수행하는 단일화된 빅데이터 스택 개발
[뉴럴 프로세싱 시스템 연구/17세부] 대규모 클러스터에서 딥러닝 학습을 자동 분산하는 시스템
비디오 튜링 테스트를 통과할 수준의 비디오 스토리 이해 기반의 질의응답 기술 개발

Barend Harris, Inpyo Bae, and Bernhard Egger. "Architectures and algorithms for on-device user customization of CNNs." In Integration, the VLSI Journal, Volume 67, July 2019.
Inpyo Bae, Barend Harris, Hyemi Min, and Bernhard Egger. "Auto-Tuning CNNs for Coarse-Grained Reconfigurable Array-based Accelerators." Presented at the 2018 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'18) and in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume 37, Issue, 11; November 2018.
Younghyun Cho, Surim Oh, and Bernhard Egger. "Performance Modeling of Parallel Loops on Multi-Socket Platforms using Queueing Systems." In IEEE Transactions on Parallel and Distributed Systems (TPDS), Volume 31, Issue 2; February 2020.
Younghyun Cho, Camilo A.C. Guzman, and Bernhard Egger. "Maximizing System Utilization via Parallelism Management for Co-Located Parallel Applications." In Proceedings of the the 2018 International Conference on Parallel Architectures and Compilation (PACT'18), Limassol, Cyprus, November 2018.
Changyeon Jo, Youngsu Cho, and Bernhard Egger. "A Machine Learning Approach to Live Migration Modeling." In Proceedings of the 2017 ACM Symposium on Cloud Computing (SoCC'17), Santa Clara, USA, September 2017.
Efficient Mapping and Scheduling of Resource and Dataflow for NPU Architecture Search, 삼성전자, 2020
Exploring the Effect of Data Compression on Runtime and Accuracy of DNNs, SK텔레콤, 2018-2020
H/W–컴파일러 수직적 통합 최적화된 임베디드 DNN 프로세서연구, 삼성전자, 2017-2020

Tae Jun Ham, Seonghak Kim, and Sung Jun Jung, Young H. Oh, Yeonhong Park, Yoon Ho Song, Junghoon Park, Sanghee Lee, Kyoung Park, Jae W. Lee, and Deog-Kyoon Jeong, "A3: Accelerating Neural Network Attention Mechanism with Approximation", 26th IEEE International Symposium on High Performance Computer Architecture (HPCA), San Diego, California, February 2020.
Shine Kim, Jonghyun Bae, Hakbeom Jang, Wenjing Jin, Jeonghun Gong, Seungyeon Lee, Tae Jun Ham, and Jae W. Lee, "SSDStreamer: Specializing I/O Stack for Large-Scale Machine Learning", IEEE Micro, September/October 2019.
Young H. Oh, Quan Quan, Daeyeon Kim, Seonghak Kim, Jun Heo, Jaeyoung Jang, Sung Jun Jung, and Jae W. Lee, "A Portable, Automatic Data Quantizer for Deep Neural Networks", IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT-27), Limassol, Cyprus, November 2018.
Channoh Kim, Jaehyeok Kim, Sungmin Kim, Dooyoung Kim, Namho Kim, Gitae Na, Young H. Oh, Hyeon Gyu Cho, and Jae W. Lee, "Typed Architectures: Architectural Support for Lightweight Scripting", 22nd ACM Architectural Support for Programming Languages and Operating Systems (ASPLOS), Xi'an, China, April 2017.
Doo Young Kim, Jin Min Kim, Hakbeom Jang, Jinkyu Jeong, and Jae W. Lee, "A Neural Network Accelerator for Mobile Application Processors", IEEE Transactions on Consumer Electronics, 61(4), November 2015.
NAND 플래시 기반 심층신경망 학습 시스템, 연구재단, 2020.3-2023.2
뉴럴 프로세싱 시스템 연구, 삼성전자, 2017.11-2020.10
Beyond Limit, 삼성전자, 2018.11-2021.10

J. Park, J. Lee, and D. Jeon, “A 65-nm Neuromorphic Image Classification Processor With Energy-Efficient Training Through Direct Spike-Only Feedback,” IEEE Journal of Solid-State Circuits (JSSC), 2020.
S. Moon, K. Shin, and D. Jeon, “Enhancing Reliability of Analog Neural Network Processors,” IEEE Transactions on VLSI Systems (TVLSI), 2019.
J. Park, Y. Kwon, Y. Park, and D. Jeon, “Microarchitecture-Aware Code Generation for Deep Learning on Single-ISA Heterogeneous Multi-Core Mobile Processors,” IEEE Access, 2019.
D. Jeon, Q. Dong, Y. Kim, X. Wang, S. Chen, H. Yu, D. Blaauw, and D. Sylvester, “A 23-mW Face Recognition Processor with Mostly-Read 5T Memory in 40-nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC), 2017.
D. Jeon, N. Ickes, P. Raina, H.-C. Wang, and A. P. Chandrakasan, “A 0.6V, 8mW 3D Vision Processor for a Navigation Device for the Visually Impaired,” IEEE International Solid-State Circuits Conference (ISSCC), 2016.
자가 학습이 가능한 초저전력 혼성신호 뉴로모픽 프로세서 설계, 과학기술정보통신부, 2019~2022.
고효율 딥러닝 하드웨어 가속기 개발, 한국과학기술연구원, 2019~2021.
모바일 시스템을 위한 저전력 머신 러닝 하드웨어 가속기 개발, 과학기술정보통신부, 2016~2019.

An efficient charge recovery logic circuit
An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance
Design of PLL-based clock generation circuits
A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL
A 0.18-μm CMOS 3.5-Gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method